Design Verification Engineer - Interface IP

Company: Etched
Location: San Jose
Posted on: February 16, 2026

Job Description:

Job Description Job Description About Etched Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history Job Summary We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. Key responsibilities End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors Understand vendor IP configurations and handle handshake with internal IP team Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications. Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture. Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios. You may be a good fit if you have 5 years of design verification experience You enjoy digging deep into complex verification challenges and finding creative ways to expose corner-case bugs. You have hands-on experience with industry-standard verification methodologies like SystemVerilog/UVM and understand how to build scalable, reusable testbenches. You are comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs. You thrive in a fast-paced startup environment and can take ownership of projects with minimal direction. You collaborate naturally with cross-functional teams — from RTL design to software and emulation — and can clearly communicate technical insights. Strong candidates may also have experience with (Nice-to-have qualifications) Experience handling vendors and integration of IP/VIP’s UVM/System Verilog Benefits Medical, dental, and vision packages with generous premium coverage $500 per month credit for waiving medical benefits Housing subsidy of $2k per month for those living within walking distance of the office Relocation support for those moving to San Jose (Santana Row) Various wellness benefits covering fitness, mental health, and more Daily lunch dinner in our office How we’re different Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs. We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed. Compensation Range: $150K - $275K

Keywords: Etched, San Mateo , Design Verification Engineer - Interface IP, Engineering , San Jose, California