Design Engineer
Company: Vertisystem Inc.
Location: San Mateo
Posted on: October 11, 2020
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Job Description:
Duties IP integration Bring-up and debug the platform issues
Write the testplan to meet ASIC pre-silicon and post-silicon
verification and validation goals including scenarios, corner
cases, performance, etc. Write testcases (SystemVerilog and C
bases), execute and debug the failures on emulation platforms
Skills - Hardware Emulation Platforms and tools - RTL development
(VerilogSystemVerilogVHDL) - Simulation acceleration knowledge (DPI
and Transactors) - Gate-level understanding of RTL and Synthesis -
Logic simulation VCSNCSIM - Programmingscripting skills (C, C++,
Python) - Software Debug tools (e.g. JTAGLauterbachGDB) - Excellent
communication skills, and ability to work in a fast-paced exciting
environment Education Bachelor's in EECSCE with 4 yearsrsquo
experience. Click below to apply or feel free to reach us at
510-804-3414
Keywords: Vertisystem Inc., San Mateo , Design Engineer, Other , San Mateo, California
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