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Physical Design Engineer with UPF/Timing/Constraints

Company: Radiansys, Inc.
Location: San Mateo
Posted on: November 14, 2020

Job Description:

Hi, Please find an urgent requirement contract for a Full-time role. Please respond ASAP with your profile Role Physical Design Engineer with UPFTimingConstraints Location Menlo Park, CA Onsite Duration Full-time role Job Description Job Description Skill Requirement IMPORTANT INFORMATION What are the top 3 "must have non-negotiable" skill sets that need to be present on a resume? Place Route, UPFLow Power Implementation, Floor planning with SYNOPSYS ICC2 Are there any specific certifications, educational background or portfolios that yoursquore looking for? Must be familiar with Synopsys Tool Set Are you open to candidates who can only work remote? Yes Duties Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes. Resolve design and flow issues related to physical design, identify potential solutions, and drive execution Deliver physical design of end-to-end IPs and SoCs. Skills MANDATORY SCREENING QUESTIONS 1) What are the typical block sizegate countfrequency you have handled and what are the challenges at that nodeprocess? 2) Any LP IPrsquos or cores you have handled? Please walk me through some of the POWER related issues you have faced in the design and how have you resolved them? Skills Experience in sub-10nm ASIC synthesis, Design for Test (DFT), Floorplan, Place Route (PnR or PR), Static Timing Analysis (STA), Low Power Intent (UPFCPF) and Power Analysis Synthesis, PnR and Timing Closures for ASIC deliverables in sub-10 nm geometries with very low power targets using tools such as Synopsys DCICC2PT. Scripting language experience including Python, PERL and TCL. Other languages are a plus. Education Bachelor's degree in Electrical Engineering, with 5 years of relevant physical design experience Required Skills PHYSICAL DESIGN, SYNOPSYS, SCRIPTING, POWER ANALYSIS, ASIC Additional Skills DESIGN ENGINEER, PYTHON, SOCS, PERL, IPS, IR, ANALOG SILICON, APPLICATION-SPECIFIC INTEGRATED CIRCUIT, ELECTRICAL ENGINEERING Thanks Regards Hardeep Kamboj Senior Technical Recruiter RADIANSYS INC DeskEXT 1003 Text 408-766-2197 Email -

Keywords: Radiansys, Inc., San Mateo , Physical Design Engineer with UPF/Timing/Constraints, Other , San Mateo, California

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